Internally funded project
Start date : 01.09.2021
Vertical power devices based on GaN-on-Si(111) potentially offer several advantages over their lateral counterpart, i.a., superior thermal management, higher reliability, and the capability of achieving high breakdown voltage and current density without increasing the chip size [1]. In addition, Si is attractive, due to the large diameter availability, low cost and good thermal conductivity compared to other substrates. However, for device operation at high voltage (> 1 kV), several micrometers of high quality GaN must be deposited. This is a major challenge as lattice and thermal mismatch lead to severe wafer curvature and eventually cracks if not properly controlled. Further, a wafer bow < ±50 µm is required for processing in a conventional CMOS line [2]. In case of substrate diameters beyond the state of the art this issue becomes even more critical, since the bow typically increases with the square of the wafer diameter. Recently the market trend for GaN-on-Si(111) is moving from 150 mm to 200 mm and development towards 300 mm is visible. Thus, a further optimized epitaxy and a model to predict the wafer bow is essential.
The target of this thesis is to provide GaN-on-Si(111) epi-stacks grown on 8” substrates which have the desired properties to fabricate power transistors with a breakdown voltage of ~1200V and a specific on-resistance of < 4 mΩ cm2. In addition, a curvature model will be developed to predict the curvature evolution during growth and after cooling based on the epitaxy process.
[1] Y. Zhang, M. Sun, Z. Liu, D. Piedra, H. Lee, F. Gao, T. Fujishima, T. Palacios, IEEE Trans. Electron Devices, 60, 2224–2230 (2013).
[2] M. Ishida, T. Ueda, T. Tanaka, D. Ueda, IEEE Trans. Electron Devices, 60, 3053–3059 (2013).