Internally funded project
Acronym: BUILDABONG
Start date : 01.10.1998
End date : 31.01.2009
Website: https://www.cs12.tf.fau.de/forschung/projekte/buildabong
In this project we consider the problems of conception and compiler support for application-specific instruction-set processors (ASIPs). Examples of such processors are digital signal processors (DSPs) and microcontrollers. Treated are the challenging problems of systematic design and simulation of application-specific processors and the development and exploration of better compilation methods to support them.
In the course of this project the tool ArchitectureComposer has been developed. The designer chooses from a library customizable building blocks to compose graphically his desired architecture. This is done by connecting instantiated components with each other. The library contains a lot of necessary building blocks for the processor design such as register files, memories, multiplexers, arithmetic and logic units, busses, and others. If necessary, it might be extended by further modules like caches, special interconnect structures, etc. All components are parametric, e.g., the word width of the modules can be chosen arbitrarily. Realistic microprocessors such as a MIPS processor or a DSP from Texas Instruments TMS320C6 series have been successfully modeled within hours.
ArchitectureComposer offers a hierarchical architecture entry to handle complex systems and to reuse already designed subsystems. Furthermore, HDL-generators allow the direct synthesis of microprocessors out of their graphical description. Generators for VHDL and Verilog are available. A generator for the specification language SystemC is currently being developed.
From the graphical architecture description a mixed structural/behavioral model of the architecture is generated automatically. This model is based on the formalism of Abstract State Machines (ASM). Additionally, a debugging and simulation environment which allows verifying the functionality of the given architecture on pipeline-cycle accurate and instruction-cycle accurate levels can be generated. Compared to existing microprocessor simulators a dedicated simulator is generated for a given architecture. This simulator offers several convenient features like traces, breakpoints and other profiling functions. Since the microprocessors’ behavior can be described in a compact form by ASMs, a substantial increase of the simulation speed can be achieved. To increase the simulation performance even more, we currently investigate the automatic generation of C++-based compiled simulators which exploit efficient graph partitioning and BDD strategies.
Modern microprocessors allow the parallel execution of several instructions on a number of functional units. Thus, compilers must be able to support this parallel execution, to build so-called very long instruction words (VLIW), and during compilation from high-level languages to assembly code, they must be able to analyze the data dependencies to generate efficient parallel code. Therefore, the compiler needs information of the architecture’s properties which are automatically extracted from the graphic entry. We use a retargetable ANSI C compiler with a set of sophisticated transformations, for instance, dead code elimination, variable propagation, loop unrolling, and a lot more. During code creation, an assembler program is generated from the information of the available functional units and the resource allocation.
During the composition of processors and their compilers, architecture changes with according compiler modifications can be analyzed in an exploration loop. Here, an exploration methodology has been developed for walking through the complex design space of architecture and compiler parameters returning the best architecture/compiler co-design solutions for a given application class (benchmark) to fulfill given constraints, e.g., code size, execution time, hardware resources, etc.
In this project we consider the problems of conception and compiler support for application-specific instruction-set processors (ASIPs). Examples of such processors are digital signal processors (DSPs) and microcontrollers. Treated are the challenging problems of systematic design and simulation of application-specific processors and the development and exploration of better compilation methods to support them.
In the course of this project the tool ArchitectureComposer has been developed. The designer chooses from a library customizable building blocks to compose graphically his desired architecture. This is done by connecting instantiated components with each other. The library contains a lot of necessary building blocks for the processor design such as register files, memories, multiplexers, arithmetic and logic units, busses, and others. If necessary, it might be extended by further modules like caches, special interconnect structures, etc. All components are parametric, e.g., the word width of the modules can be chosen arbitrarily. Realistic microprocessors such as a MIPS processor or a DSP from Texas Instruments TMS320C6 series have been successfully modeled within hours.
ArchitectureComposer offers a hierarchical architecture entry to handle complex systems and to reuse already designed subsystems. Furthermore, HDL-generators allow the direct synthesis of microprocessors out of their graphical description. Generators for VHDL and Verilog are available. A generator for the specification language SystemC is currently being developed.
From the graphical architecture description a mixed structural/behavioral model of the architecture is generated automatically. This model is based on the formalism of Abstract State Machines (ASM). Additionally, a debugging and simulation environment which allows verifying the functionality of the given architecture on pipeline-cycle accurate and instruction-cycle accurate levels can be generated. Compared to existing microprocessor simulators a dedicated simulator is generated for a given architecture. This simulator offers several convenient features like traces, breakpoints and other profiling functions. Since the microprocessors’ behavior can be described in a compact form by ASMs, a substantial increase of the simulation speed can be achieved. To increase the simulation performance even more, we currently investigate the automatic generation of C++-based compiled simulators which exploit efficient graph partitioning and BDD strategies.
Modern microprocessors allow the parallel execution of several instructions on a number of functional units. Thus, compilers must be able to support this parallel execution, to build so-called very long instruction words (VLIW), and during compilation from high-level languages to assembly code, they must be able to analyze the data dependencies to generate efficient parallel code. Therefore, the compiler needs information of the architecture’s properties which are automatically extracted from the graphic entry. We use a retargetable ANSI C compiler with a set of sophisticated transformations, for instance, dead code elimination, variable propagation, loop unrolling, and a lot more. During code creation, an assembler program is generated from the information of the available functional units and the resource allocation.
During the composition of processors and their compilers, architecture changes with according compiler modifications can be analyzed in an exploration loop. Here, an exploration methodology has been developed for walking through the complex design space of architecture and compiler parameters returning the best architecture/compiler co-design solutions for a given application class (benchmark) to fulfill given constraints, e.g., code size, execution time, hardware resources, etc.