Dedizierte massiv parallele Systeme (PARO)
Internally funded project
Acronym:
PARO
Start date :
03.01.2000
Website:
https://www.cs12.tf.fau.de/forschung/projekte/paro
Regular Mapping for Coarse-grained Reconfigurable Architectures (2004)
Hannig F, Dutta H, Teich J
Conference contribution
Dynamic Piecewise Linear/Regular Algorithms (2004)
Hannig F, Teich J
Conference contribution
Automatic and Optimized Generation of Compiled High-Speed RTL Simulators (2004)
Hannig F, Kupriyanov O, Teich J
Conference contribution
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals (2004)
Hannig F, Teich J
Conference contribution
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology (2004)
Hannig F, Dutta H, Teich J
Conference contribution
Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms (2004)
Hannig F, Teich J
Other publication type
Generation of Distributed Loop Control (2002)
Hannig F, Teich J, Bednara M
Book chapter / Article in edited volumes
Interface Synthesis for FPGA Based VLSI Processor Arrays (2002)
Bednara M, Teich J
Conference contribution
Energy Estimation for Piecewise Regular Processor Arrays (2002)
Hannig F, Teich J
Conference contribution
Energy Estimation of Nested Loop Programs (2002)
Hannig F, Teich J
Conference contribution