PD Dr.-Ing. Frank Hannig

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Hardware cost analysis for weakly programmable processor arrays (2006) Kissler D, Hannig F, Kupriyanov O, Teich J Conference contribution, Conference Contribution MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I (2006) Kupriyanov O, Hannig F, Kissler D, Schaffer R, Teich J Other publication type Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology (2006) Dutta H, Hannig F, Teich J Journal article Controller Synthesis for Mapping Partitioned Programs on Array Architectures (2006) Dutta H, Hannig F, Teich J Conference contribution Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints (2006) Dutta H, Hannig F, Teich J Conference contribution Hierarchical Partitioning for Piecewise Linear Algorithms (2006) Dutta H, Hannig F, Teich J Conference contribution Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays (2006) Hannig F, Merker R, Siegel S, Teich J Conference contribution A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing (2006) Dutta H, Hannig F, Heigl B, Hornegger H, Teich J Conference contribution A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template (2006) Kissler D, Hannig F, Kupriyanov O, Teich J Conference contribution A highly parameterizable parallel processor array architecture (2006) Kissler D, Kupriyanov O, Hannig F, Teich J Conference contribution, Conference Contribution