PD Dr.-Ing. Frank Hannig

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Impact of loop tiling on the controller logic of acceleration engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution, Conference Contribution Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures (2009) Kissler D, Strawetz A, Hannig F, Teich J Journal article A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors (2009) Dutta H, Kissler D, Hannig F, Kupriyanov O, Teich J, Pottier B Journal article Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis (2009) Dutta H, Hannig F, Teich J Conference contribution Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance (2009) Lari V, Hannig F, Teich J Conference contribution Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning (2009) Hannig F, Dutta H, Teich J Conference contribution Optimization Flow for Algorithm Mapping on Graphics Cards (2009) Membarth R, Hannig F, Dutta H, Teich J Conference contribution FSM-Controlled Architectures for Linear Invasion (2009) Arifin F, Membarth R, Amouri A, Hannig F, Teich J Conference contribution Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors (2009) Membarth R, Hannig F, Dutta H, Teich J Conference contribution