PD Dr.-Ing. Frank Hannig

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays (2015) Teich J, Boppu S, Hannig F, Lari V Book chapter / Article in edited volumes Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays (2015) Sousa É, Hannig F, Teich J, Schlichtmann U, Chen Q Conference contribution, Conference Contribution Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures (2015) Roloff S, Schafhauser D, Hannig F, Teich J Conference contribution, Conference Contribution A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays (2015) Lari V, Tanase AP, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B Conference contribution, Conference Contribution Automatic Optimization of Hardware Accelerators for Image Processing (2015) Reiche O, Häublein K, Reichenbach M, Hannig F, Teich J, Fey D Conference contribution Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015) (2015) Hannig F, Koch D, Ziener D Edited Volume Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays (2015) Sousa É, Hannig F, Teich J Conference contribution On-demand fault-tolerant loop processing on massively parallel processor arrays (2015) Tanase AP, Witterauf M, Teich J, Hannig F, Lari V Conference contribution, Conference Contribution Loop Coarsening in C-based High-Level Synthesis (2015) Schmid M, Reiche O, Hannig F, Teich J Conference contribution, Conference Contribution Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (2015) Hannig F, Fey D, Lokhmotov A Edited Volume