Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford-PKU Model (2020) Reuben JR, Biglari M, Fey D Journal article Understanding HPC benchmark performance on intel broadwell and cascade lake processors (2020) Alappat C, Hofmann J, Hager G, Fehske H, Bishop AR, Wellein G Conference contribution The allscale framework architecture (2020) Jordan H, Gschwandtner P, Thoman P, Zangerl P, Hirsch A, Fahringer T, Heller T, Fey D Journal article Memristoren für zukünftige Rechnersysteme (2020) Fey D, Karl W, Ungerer T Journal article mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck (2020) Talati N, Ben-Hur R, Wald N, Haj-Ali A, Prabahar JR, Kvatinsky S Book chapter / Article in edited volumes Simulating memristive systems in mixed-signal mode using commercial design tools (2019) Fritscher M, Knödtel J, Reichenbach M, Fey D Conference contribution A Hardware Inference Accelerator for Temporal Convolutional Networks (2019) Ali R, Mallah M, Leyh M, Holzinger P, Breiling M, Reichenbach M, Fey D Conference contribution, Conference Contribution A First-Principles Approach to Performance, Power, and Energy Models for Contemporary Multi- and Many-Core Processors (2019) Hofmann J Thesis A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM (2019) Reuben JR, Fey D Conference contribution System architecture for network-attached FPGAs in the cloud using partial reconfiguration (2019) Ringlein B, Abel F, Ditter A, Weiss B, Hagleitner C, Fey D Conference contribution