Lehrstuhl für Informatik 3 (Rechnerarchitektur)

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms (2021) Hosseinzadeh S, Biglari M, Fey D Journal article Design of in-memory parallel-prefix adders (2021) Reuben JR Journal article A low-power rram memory block for embedded, multi-level weight and bias storage in artificial neural networks (2021) Pechmann S, Mai T, Potschka J, Reiser D, Reichel P, Breiling M, Reichenbach M, Hagelauer A Journal article Opening the Black Box: Performance Estimation during Code Generation for GPUs (2021) Ernst D, Hager G, Holzer M, Knorr M, Wellein G Conference contribution, Conference Contribution A Case for Function-As-A-Service with Disaggregated FPGAs (2021) Ringlein B, Abel F, Diamantopoulos D, Weiss B, Hagleitner C, Reichenbach M, Fey D Conference contribution Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles (2021) Prabahar JR, Fey D Conference contribution E = AI(2) (2021) Breiling M, Kundu B, Reichenbach M Journal article RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems (2021) Reichenbach M, Knödtel J, Rachuj S, Fey D Journal article Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems (2021) Perez-Bosch Quesada E, Romero-Zaliz R, Perez E, Kalishettyhalli Mahadevaiah M, Reuben JR, Schubert MA, Jimenez-Molinos F, et al. Journal article A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells (2021) Pechmann S, Mai T, Völkel M, Mahadevaiah MK, Perez E, Quesada EPB, Reichenbach M, et al. Journal article