Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism (2005) Mostaghim S, Teich J Book chapter / Article in edited volumes Automatic FIR Filter Generation for FPGAs (2005) Dutta H, Hannig F, Teich J Conference contribution A system-level approach to hardware reconfigurable systems (2005) Haubelt C, Otto S, Grabbe C, Teich J Conference contribution, Conference Contribution Defragmenting the Module Layout of a Partially Reconfigurable Device (2005) Ahmadinia A, Bobda C, Fekete SP, Hannig F, Majer M, Teich J, Van Der Veen JC Conference contribution Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures (2005) Dutta H, Hannig F, Teich J Other publication type The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform (2005) Ahmadinia A, Bobda C, Fekete SP, Haller T, Linarth AG, Majer M, Teich J, Van Der Veen JC Conference contribution Output Serialization for FPGA-based and Coarse-grained Processor Arrays (2005) Hannig F, Teich J Conference contribution Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine (2005) Ahmadinia A, Bobda C, Haller T, Linarth AG, Majer M, Teich J Conference contribution A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices (2005) Ahmadinia A, Bobda C, Ding J, Fekete SP, Majer M, Teich J, Van Der Veen JC Conference contribution Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke (2005) Streichert T, Haubelt C, Teich J Conference contribution