Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template (2006) Kissler D, Hannig F, Kupriyanov O, Teich J Conference contribution Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms (2006) Schlichter T, Lukasiewycz M, Haubelt C, Teich J Conference contribution, Conference Contribution A highly parameterizable parallel processor array architecture (2006) Kissler D, Kupriyanov O, Hannig F, Teich J Conference contribution, Conference Contribution Higher-dimensional packing with order constraints (2006) Teich J, Fekete SP, Köhler E Journal article Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms (2006) Haubelt C, Schlichter T, Teich J Journal article Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays -- Architectural Parameters and Methodology (2006) Hannig F, Dutta H, Teich J Journal article Online Placement for Dynamically Reconfigurable Devices (2006) Ahmadinia A, Bobda C, Teich J Journal article Analysis of Dataflow Programs with Interval-limited Data-rates (2006) Bhattacharyya SS, Teich J Journal article Automatic Test Generation with Model Checking Techniques (2006) Schneider A, Bunin G, Haubelt C, Heinkel U Conference contribution A Generic Framework for Rapid Prototyping of System-on-Chip Designs (2006) Kissler D, Kupriyanov O, Hannig F, Koch D, Teich J Conference contribution