Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices (2008) Dutta H, Hannig F, Ruckdeschel H, Teich J Conference contribution PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications (2008) Hannig F, Ruckdeschel H, Dutta H, Teich J Conference contribution Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution No-Break Dynamic Defragmentation of Reconfigurable Devices (2008) Fekete SP, Kamphans T, Schweer N, Tessars C, Van Der Veen JC, Angermeier J, Koch D, Teich J Conference contribution Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs (2008) Schmid M, Ziener D, Teich J Conference contribution Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads (2008) Angermeier J, Teich J Conference contribution Concepts for Autonomous Control Flow Checking for Embedded CPUs (2008) Ziener D, Teich J Conference contribution Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs (2008) Angermeier J, Hanke S, Majer M, Teich J, Wildermann S Conference contribution A Sequential Learning Resource Allocation Network for Image Processing Applications (2008) Teich J, Wildermann S Conference contribution