Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor (2014) Glein R, Schmidt B, Rittner F, Teich J, Ziener D Conference contribution, Conference Contribution Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach (2014) Hannig F, Lari V, Boppu S, Tanase AP, Reiche O Journal article An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (2014) Schmidt B, Ziener D, Teich J Conference contribution Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning (2014) Xu Y, Wang B, Teich J Conference contribution Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration (2014) Becher A, Bauer F, Ziener D, Teich J Conference contribution, Conference Contribution High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model (2014) Schmid M, Hannig F, Tanase AP, Teich J Book chapter / Article in edited volumes Compact Code Generation for Tightly-Coupled Processor Arrays (2014) Boppu S, Hannig F, Teich J Journal article Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computer (2013) Angermeier J Thesis Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling (2013) Gladigau J Thesis Scenario-Based Energy Estimation of Heterogeneous Integrated Systems at System Level (2013) Glock S, Rosales R, Reutelhuber F, Glaß M, Teich J, Fischer G, Weigel R, Ußmüller T Conference contribution