Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Timing Verification of Realtime Automotive Networks: What can we expect from Simulation? (2016) Navet N, Seyler J, Migge J Conference contribution ActorX10: An Actor Library for X10 (2016) Roloff S, Pöppl A, Schwarzer T, Wildermann S, Baader M, Glaß M, Hannig F, Teich J Conference contribution Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures (2016) Häublein K, Reichenbach M, Reiche O, Özkan MA, Fey D, Hannig F, Teich J Conference contribution LoopInvader: A Compiler for Tightly Coupled Processor Arrays (2016) Tanase AP, Witterauf M, Sousa É, Lari V, Hannig F, Teich J Conference contribution Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016 (2016) Fanucci L, Teich J Book chapter / Article in edited volumes Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays (2016) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution Supporting Composition in Symbolic System Synthesis (2016) Haubelt C, Neubauer K, Glaß M Conference contribution Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design (2016) Wang B, Xu Y, Hasholzner R, Drewes C, Rosales R, Graf S, Falk J, et al. Conference contribution Invasive Computing for Timing-Predictable Stream Processing on MPSoCs (2016) Wildermann S, Bader M, Bauer L, Damschen M, Gabriel D, Gerndt M, Glaß M, et al. Journal article Recap of the 2016 DATE Conference & Exhibition (2016) Fanucci L, Teich J Journal article