Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Environment Mapping Using Massively Parallel Architectures (2017) Fickenscher J, Bouzouraa ME, Hannig F, Teich J Conference contribution, Abstract of a poster Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays (2017) Tanase AP, Witterauf M, Teich J, Hannig F Journal article, Original article High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems (2017) Streit FJ, Letras M, Schid M, Falk J, Wildermann S, Teich J Conference contribution, Conference Contribution Generating FPGA-based Image Processing Accelerators with Hipacc (2017) Reiche O, Özkan MA, Membarth R, Teich J, Hannig F Conference contribution, Conference Contribution Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders (2017) Echavarria Gutiérrez JA, Wildermann S, Potwigin E, Teich J Journal article, Original article System-Level Reliability Analysis Considering Imperfect Fault Coverage (2017) Khosravi F, Aliee H, Teich J Conference contribution, Conference Contribution Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems (2017) Pourmohseni B, Wildermann S, Glaß M, Teich J Conference contribution, Conference Contribution Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers (2017) Kuckuk S, Leitenmaier L, Schmitt C, Schönwetter D, Köstler H, Fey D Other publication type A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis (2017) Özkan MA, Reiche O, Hannig F, Teich J Conference contribution Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing (2017) Özkan MA, Reiche O, Hannig F, Teich J Conference contribution