A parallel-friendly majority gate to accelerate in-memory computation (2020) Reuben JR, Pechmann S Conference contribution Domain-Specific Augmentations for High-Level Synthesis (2014) Schmid M, Tanase AP, Hannig F, Teich J, Bhadouria VS, Ghoshal D Conference contribution Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays (2013) Teich J, Tanase AP, Hannig F Conference contribution Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators (2013) Boppu S, Hannig F, Teich J Conference contribution Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays (2011) Lari V, Narovlyanskyy A, Hannig F, Teich J Conference contribution Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (2011) Cavallaro JR, Ercegovac MD, Hannig F, Ienne P, Swartzlander Jr. EE, Tenca AF Edited Volume A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing (2006) Dutta H, Hannig F, Heigl B, Hornegger H, Teich J Conference contribution Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals (2004) Hannig F, Teich J Conference contribution